1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for accelerating the transfer of data being read from memory across a bridge joining two buses in a computer system.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units such as the 8088, 8086, 80186, 80286, i386.TM., and i486.TM. microprocessors designed and manufactured by Intel Corporation of Santa Clara, Calif. (herein referred to as the Intel processors), such buses have typically been designed as either an Industry Standard Architecture (ISA) bus or an Expanded Industry Standard Architecture (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. Each of these buses functions at a frequency of eight megahertz. The data transfer rates provided by these bus widths and operational frequencies have been found limiting so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds that more closely approximate the speed at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card for an output display device) are joined to this faster local bus. However, it is most desirable to be able to continue to utilize those components which were designed to operate with the older buses and which operate at a slower rate. In order to do this, the slower ISA or EISA bus is maintained in essentially unchanged form; and those components which are able to tolerate longer access times are associated with the slower bus. It is then necessary to provide arrangements by which data may be transferred between all of the computer system components. This requires complicated interfacing arrangements. Although the theory behind using a local bus is good, many local bus designs have created conflicts in accessing components which actually slow the operation of the computer.
Intel Corporation has designed a new local bus which may be used in a computer system including other buses such as an ISA bus or an EISA bus (which are hereinafter referred to broadly as secondary buses). This new local bus provides faster throughput of data for selected components of the system without the conflicts which arise using other local bus systems. This new bus is referred to as the "peripheral component interconnect" (PCI) bus. A computer system using this PCI bus includes in addition to the physical PCI bus a first bridge circuit which provides the interface and controls the transfer of data among the PCI bus, the central processing unit, and main memory. A second bridge circuit is also provided as an interface between and a control for the transfer of data between a secondary bus and the PCI bus. Thus, the arrangement is such that components on the PCI bus transfer data to and receive data from main memory through the first bridge which joins to the central processor and to the main memory; while components on the secondary bus transfer and receive data through the second bridge and through the PCI bus for transfers with components on the PCI bus, and through the first and second bridges and the PCI bus for transfers with the central processor and the main memory.
Various designs of secondary bridges have been proposed. Specific embodiments of such bridges are described in detail in a publication entitled 82420/82430 PCIset, ISA and EISA Bridges, 1993, Intel Corporation. The design of these bridges is controlled by various factors relating to the design of each of the PCI and secondary buses. The PCI bus has been designed as a thirty-two bit bus. The PCI bus joins to the central processing unit and main memory through the first bridge circuit which is designed to buffer transfers of data so that a faster processor need not slow to the speed of the bus in transferring data. Similarly, the secondary bridge and each other bridge which is connected to the PCI bus provides buffering so that transfers of data in either direction may be accelerated.
Buffering greatly enhances the speed of data transfer in the computer system. For example, buffering in the first bridge circuit allows a CPU operating at a higher data transfer rate than the PCI bus to store data in the bridge and continue with other operations while the bridge completes the transfer of stored data. Buffering in the second bridge circuit which joins the two buses also offers substantial advantages. For example, when a bus master on a faster bus is trying to write to a slower bus without buffering, the speed of the transfer necessarily slows to the speed at which the slower bus can accept the data. When transferring in the other direction to the faster bus without buffering, the speed of transfer to the faster bus can only approach the speed at which the components on the slower bus are able to transfer data.
However, data buffering in the bridge circuits also poses a number of problems. One problem which has arisen with integrating the newer PCI bus into a computer system with the older secondary buses is that data being read from main memory and transferred across the bridge circuit between the buses is slowed by the need enforced by the PCI protocol to arbitrate for access to the PCI bus with each increment of data transferred. Direct memory access (DMA) devices are used so that the central processor does not have to accomplish all of the individual transfers necessary in a computer system. Typically, a direct memory access (DMA) device resides on the secondary bus and is used to transfer large amounts of data at sequential addresses to or from main memory. Since the primary use of the bridge is to transfer data to and from devices on the different buses, and since main memory lies on the PCI side of the second bridge while all secondary devices lie on the secondary bus side of the bridge, each access of main memory by the DMA device is time consuming. When a DMA device on the secondary bus is reading from main memory, it must arbitrate for the secondary bus, acquire that bus, arbitrate for the PCI bus, acquire that bus, access memory at a first address, read the increment of data (which is typically thirty-two bits) into a bridge buffer, and then read the data from the bridge buffer to its destination. However, because the secondary bridge is not aware of what data the bus master will next require, the bridge as a PCI bus master may either relinquish the PCI bus after each access or continue to wait on the PCI bus until the next DMA access. Since waiting on the bus is a waste of the PCI bandwidth, the bridge relinquishes the bus after each such access. Consequently, the DMA must immediately begin arbitrating for the PCI bus again for the next thirty-two bit increment of data. This process takes an inordinate amount of time. The problem is exacerbated since the DMA device on the secondary bus cannot be forced off the secondary bus until it has completed its operations. This makes it impossible to complete transfers from other PCI masters to the secondary bus while the DMA has access to the secondary bus and slows operations on the PCI bus.
Consequently, it is very desirable to increase the speed of DMA read operations from main memory across the second bridge in a computer system using a PCI bus and a secondary bus.